application note j.nicolai a AN592 / 03,93 pll generation using st62 auto-reload timer figure 1. auto-reload timer block diagram introduction this note describes how to generate a digital signal locked in phase and frequency (pll) with a c alibrated delay starting from an active edge on the auto-reload timer input pin. auto-reload timer description this timer is an 8 bit timer/counter with prescaler. it includes auto-reload pwm, capture and compare ca- pability with one input and one output pins. it can be controlled by the following registers (8 bit): - mode control register (mc) - status registers (sc0, sc1) - load register (lr) - incremental counter register (tc) - compare register (cp) - reload/capture register (rc) it can also wake-up the mcu from wait mode and exit from stop mode if an external event is present on the input pin. the prescaler ratio can be programmed to choose the timer input frequency f in (see table 1). 1/4
bit 0 reg. sc1 ps2 ps1 ps0 prescaler ratio 0 000 1 0 001 2 0 010 4 0 011 8 0 100 16 0 101 32 0 110 64 0 111 128 1 000 3 1 001 6 1 010 12 1 011 24 1 100 48 1 101 96 1 110 192 1 111 384 table 1. prescaler programming ratio example: the timin input receives a 15 khz digital signal. we want to generate a phase-locked 15 khz digital signal with a falling edge delayed 19 m s from the in- put rising edge, and a duty cycle of 75%. the cpu quartz frequency is 8 mhz. the figure 2 shows the timout signal generated in load on external edge mode, given the above timin signal: on timin rising edge, the tc count register is loaded with the value contained in rc register (160 in this example). the timer will re- sume counting from value 160. when the compare value (210 in this example) is reached, the ti- mout signal goes down. the timer keeps count- ing until the overflow (255) is reached. at this point, signal timout rises again. the timer keeps count- ing from 0 until next active edge on timin. at this time, tc is loaded again with the rc value (160) and so on... the delay from timin edge to timout falling edge is given by cp-rc (multiplied by the tc reg- ister clock period fin). the low level duration on ti- mout is given by 255 - cp. the remaining of the timout period is variable, and will adjust to the timin period: small variations of timin period will be absorbed by a variation of t var . the following rule must be respected in order to get the proper output signal: the variable time tvar must stay smaller than cp, (otherwise the falling edge on timout occurs be- fore rising edge on timin) and larger than 0 (other- wise the rising edge on timout never occurs). in other words, the period of input timin (tot in terms of tc clock cycles) must meet the following requirement: 255 - rc < tot < 255 - rc + cp coming back to our example, lets calculate the timer settings: the input period is tin = 1/15 khz = 66.7 m s figure 2. timout signal note: all numbers are decimal a pll generation using artimer 2/4
calculation of the prescaler ratio: we want the best possible resolution, e.g. the smaller possible prescaler ratio: we would like the tc counter to count up to the highest number: 255 (for best resolution). in this case 66.7 m s / 255 = 0.26 m s is the small- est tc clock period that we can use. with a prescaler ratio of 1, the tc clock period is 1/8mhz = 0.125 m s. so we need a prescaler ratio of 3, giving a tc clock period of 3/8 mhz = 0.375 m s. this is the elementary incrementing time of the tc counter, which gives the resolution of the phase shift and of the low level on timout (the tc counter is incremented with a clock f in = 1/0.375 m s = 2667khz). the desired delay is 19 m s: cp - rc = 19 m s /0.375 m s = 50.67. the timin period is: tot = 66.7 m s / 0.375 m s = 177.78. the duty cycle is: 0.25 = (255 - cp)/tot rounding the decimals, this gives: rc = 160; cp = 210; tot = 178 the variable time t var is: t var = tot - 255 + rc = 83 the condition is met: tvar is positive and smaller than cp: (255 - 160) < 178 < (255 - 160 + 210) the timout signal will remain correct and stable as long as this condition is met, even if the input fre- quency varies: the input frequency limits for output correctness are: (255 - 160) x 0.375 m s < t in < (255 - 160 + 210) x 0.375 m s the output signal will remain locked in phase and frequency as long as the input signal timin is in the range: 8.7khz < timin frequency < 28khz of course, it is also possible to modify by software the 19 m s delay and the 75% duty cycle, for example by measuring repetitively an error voltage with the a/d converter and calculating the modified delay or duty cycle. ;**************** a-r timer register set ******************* rc .def 0d9h,0ffh,0ffh ;reload/capture register cp .def 0dah,0ffh,0ffh ;compare register mc .def 0d5h,0ffh,0ffh ;mode control register sc0 .def 0d6h,0ffh,0ffh ;status/control register 0 sc1 .def 0d7h,0ffh,0ffh ;status/control register 1 lr .def 0dbh,0ffh,0ffh ;load register ;============================================================ ldi cp, 210 ;compare register = 210d ldi rc, 160 ;reload register = 160d ldi sc1,00000101b ;clock source= cpu clock divided by 3 ;rising timin edge active ;pull-up disabled, prescaler ratio = 1 ldi mc, 11100011b ;load on timin mode,interrupts disabled ;pwmout enabled, start timer program example a pll generation using artimer 3/4
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